Apalis Carrier Board Design Guide
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Positive differential USB signal, OTG capable
Negative differential USB signal, OTG capable
Positive differential receiving signal for USB3.0, OTG capable
Negative differential receiving signal for USB3.0, OTG capable
Positive differential transmission signal for USB3.0, OTG capable
Negative differential transmission signal for USB3.0, OTG capable
Cable identification pin for the OTG
Bus voltage detection in the OTG client mode
Enable signal for the bus voltage output in host mode for the
USBO1 interface
Overcurrent input signal for the USBO1 interface
Table 9: USBO1 signals
USBH2 and USBH3 ports do not provide the additional data signals for SuperSpeed USB3.0. The
power enable and overcurrent signals are shared also with the USBH4 port.
Positive differential USB host signal
Negative differential USB host signal
Enable signal for the bus voltage output, shared with all USB host
ports
Over current input signal, shared with all USB host ports
Positive differential USB host signal
Negative differential USB host signal
Enable signal for the bus voltage output, shared with all USB host
ports
Overcurrent input signal, shared with all USB host ports
Positive differential USB host signal
Negative differential USB host signal
Positive differential receiving host signal for USB3.0
Negative differential receiving host signal for USB3.0
Positive differential transmission host signal for USB3.0
Negative differential transmission host signal for USB3.0
Enable signal for the bus voltage output, shared with all USB host
ports
Overcurrent input signal, shared with all USB host ports