Figure 24: USB 3.0 host block diagram
The power enable signal USBH_EN is shared with the other two host interfaces USBH2 and USBH3.
If the USB bus power supply needs to be switched individually for each port, any free pin with
GPIO functionality could be used. In this case the USB driver needs to be modified to support such
an implementation.
The USBH_OC# signal is shared between all the USB host ports of the Apalis. Since the signal is
open drain type, it can be connected directly to the all overcurrent output ports. The signal requires
a pull-up resistor on the carrier board.
Figure 25: USB 3.0 host reference schematic
2.5.2.4 USB 3.0 Device Down Schematic Example
Device-Down means that the USB device is soldered to the carrier board. The AC coupling
capacitors for the SuperSpeed RX lane (TX from the device) need to be placed on the carrier board.
As the capacitors for the TX lane are located on the Apalis module, no additional capacitors are
required nor permitted on the TX lines.
No series capacitors should be placed in the USB 2.0 data signal lines. Instead of placing a
common mode choke to the USB 2.0 data signals, series resistors can be added for reducing the
To Next Page
Loading...
