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Apalis Carrier Board Design Guide
Toradex AG l Altsagenstrasse 5 l 6048 Horw l Switzerland l +41 41 500 48 00 l www.toradex.com l info@toradex.com
Page | 40
2.7.2.1 18-bit Color Mapping
The color mapping for the 18-bit LVDS interface is standardized and is shown in the following
picture:
Figure 35: 18-bit LVDS Color Mapping
2.7.2.2 24-bit JEIDA Color Mapping
The JEIDA color mapping is compatible with the 18-bit LVDS interface. Therefore, the mapping is
sometimes also called “24-bit / 18-bit Compatible Color Mapping”. The signal names of the color
bits are renamed (e.g. the 18-bit R5 is renamed to 24-bit R7) but the position of the MSB is kept as
the same. The additional least significant bits R0, R1, G0, G1, B0, and B1 are transmitted in the
additional fourth LVDS data pair.
Figure 36: 24-bit JEIDA LVDS color mapping
2.7.2.3 24-bit VESA Color Mapping
Most of the 24-bit LVDS displays follow the VESA Color mapping. The VESA color mapping does
not rename the signal bits. This means that the position of the MSB is different as they are
available in the additional data pair. Hence, the VESA color mapping is not compatible with the
18-bit interface.
Figure 37: 24-bit VESA LVDS color mapping
LVDS1_A_CLK+
LVDS1_B_CLK+
LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
Previous Cycle Current Cycle Next Cycle
G0 R5 R4 R3 R2 R1 R0
B1 B0 G5 G4 G3 G2 G1
DE VSYNC HSYNC B5 B4 B3 B2
LVDS1_A_CLK+
LVDS1_B_CLK+
LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
LVDS1_A_TX3+/-
LVDS1_B_TX3+/-
Previous Cycle Current Cycle Next Cycle
G2 R7 R6 R5 R4 R3 R2
B3 B2 G7 G6 G5 G4 G3
DE VSYNC HSYNC B7 B6 B5 B4
N/A B1 B0 G1 G0 R1 R0
LVDS1_A_CLK+
LVDS1_B_CLK+
LVDS1_A_TX0+/-
LVDS1_B_TX0+/-
LVDS1_A_TX1+/-
LVDS1_B_TX1+/-
LVDS1_A_TX2+/-
LVDS1_B_TX2+/-
LVDS1_A_TX3+/-
LVDS1_B_TX3+/-
Previous Cycle Current Cycle Next Cycle
G0 R5 R4 R3 R2 R1 R0
B1 B0 G5 G4 G3 G2 G1
DE VSYNC HSYNC B5 B4 B3 B2
N/A B7 B6 G7 G6 R7 R6

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