Figure 58: Shut-down sequence
When the RESET_MICO# is asserted, a reset cycle is initiated. The module internal reset and the
external reset output RESET_MOCI# are asserted as long as RESET_MICO# is asserted. If the reset
input RESET_MICO# is de-asserted, the internal reset and the RESET_MOCI# will remain low for at
least 1ms until they are also de-asserted and the module starts booting again. This guarantees a
minimum reset time of 1ms even if the reset input RESET_MICO# is triggered for a short time.
Some Apalis modules may implement a power cycle during reset.
Figure 59: Reset sequence
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