Wang 5536 - Page 29

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3402
The Data Path defines the path by which information bytes are transferred
between the serial data link and the data bus, address bus, command
register, or status register.
The workstation portion of the data link normally monitors the serial,
half-duplex transmission line. The first "l" detected by the differential
line receiver causes a timing circuit to count out the eleven-bit intervals
needed for a byte transfer. When the last bit of the serial/parallel shift
register has been loaded, line parity is tested, the first byte of
information is loaded into a command register, and a DMA bus request is
initiated. Since stray line noise may start the timing circuits, three
bits in the first byte are checked for a special header character. The
remaining bits can be decoded to indicate a conunand if and only if the
header is correct.
PARITY
TEST
r----,
I STATUS I
I REGISTER I
L.. ...J
DLS~~OIS
OLE~ __ ..._ __
DATA
IN
ADDRESS BUS
I
HI ADDRESS I LO ADDRESS
BUFFER I CENTER
PARALLEL/SERIAL
DATA
OUT
TIMING
COM-
MAND
BUFFER
DECODE
LOGIC
<=-_J--DATAeu_s -->
Figure 2-8. Data Link Block Diagram
2-15
LINE
CONTROL