Wang 5536 - Page 30

3402
After the first byte has been transmitted, data link operation depends on
the decoded command. A DATA TRANSFER command (READ or WRITE) loads the
next two bytes into the high- and low-address registers, respectively. The
low-address register is a counter that increments the DMA byte address
rollowing each trans fer. A 256:-byte trans fer connnand ends when the add Fess
counter overflqws. For WRITE operations, a data byte(s) immediately
follows the low half of the address. For READ operations, line-control
logic must reverse the half-duplex line before data can be sent to the
master. A built-in delay (8 microseconds) provides time for the line to
quiet before data is transmitted.
Non-data commands (STATUS and RESTART) do not transfer an address. RESTART
generates a 1.8 microsecond reset pulse to the Workstation CPU. STATUS
causes a Data Link Status Word to be transmitted to the Master CPU after a
line reversal.
The Master monitors each command during its execution and clears the Data
Link when the command has been completed.
Timing is normally enabled to receive data. Timing logic recognizes the
start bit preceding each byte and determines when the enttr.,~ byte has been
received. It also provides bit timing when information is transmitted to
the Master. During READ and STATUS conunands, timing logic clears timing
during line reversal and maintains continuous timing while transmitting.
Line control ensures that the Data Link is ready to receive command inputs
from the Master when the Data Link is not in use, determines that the line
is quiet before reversing the half-duplex line, generates and checks line
parity on each byte, and clears the Data Link both after each connnand and
in the event of a line failure.
Line Control logic interlocks the Data Line Drivers and Receivers to ensure
that the Workstati 'm does not transmit into itself. The Line Drivers are
disabled until they are required to transmit data or status to the Master
during a specific command.
Command Decode decodes and validates commands from the Master after a valid
command (three-bit header) has been recognized.
2.3.2.3 DMA Control
Bus Requests are generated by the Data Link when a non-processor device
requires direct memory access (DMA) for a data trans fer. DMA transfers
typically move blocks of data between main memory and mass storage
devices. DMA operations have a higher priority than CPU operations due to
real-time requirements.
Before a DMA device can use the bus it must gain control of the bus from
the CPU. The CPU permits it to do so by recognizing the presence of a Bus
Request and disabling its own bus inputs and outputs as soon as its current
machine cycle has been completed. The CPU indicates when the cycle is
complete by as"serting Bus Acknowledge. The DMA device now has control of
the bus for as long as Bus Request remains asserted.
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