Wang 5536 - Page 34

3402
2.4.3.1 USART
THE 8251A USART (Universal Synchronous/Asynchronous Receiver/Transmitter)
is programmed by the CPU to operate using 2780, 3780, WPS, TTY, or 2741
· rotocols. When the des ired protocol has been selected, the CPU sends out
a set of control words to the USART that program BAUD RATE, CHARACTER
LENGI'H, NUMBER OF STOP BITS, SYNCHRONOUS or ASYNCHRONOUS OPERATION and
EVEN/ODD/OFF/MARK/SPACE PARITY. The USART then accepts data characters
from the CPU in parallel format and then converts them into a continuous
serial data stream for transmission. Simultaneously, it can receive serial
data streams and convert them into parallel data characters for the CPU.
Internal
circuit.
an output
device timing for the USART is provided by a 2.45 MHz clock
Transmit and receive clocks are also derived from this circuit as
of 113, Pin 9.
2.4.3.2 Input/Output
During a transmit operation, data is received from the CPU 1n parallel
format by a bi-directional driver (Z80 configuration) or an LS240 Receiver
(8080 configuration). The data (D0-07) is then gated into the USART where
it is converted into serial stream format, gated to the transmit driver and
sent to the 25-pin RS-232-C connector interface.
During a receive operation, data is received by the RS-232 r!ce1ve
circuitry rn serial stream format and gated into the USART where it is
converted into parallel format. The data is then gated through either a
bi-directional driver (Z80 configuration) or 368 type drivers (8080
configuration) to the CPU Data Bus.
2.4.3.3 "In"/"Out" Decoding
The CPU uses "IN" and "OUT" conunand instructions to send or receive control
or status information to or from the TC PCA. These instructions are
described individually in the following sections. When setting control
bits and reading status bits, a logical ON condition is represented by a
"l" bit, and a logical OFF condition is represented by a "O" bit.
Read Modem Status Signals
Instruction IN X '02'
BIT MEANING
DO RLS
Dl
SRL
D2 DSR
D3 CTS
D4 RD
The status signals from the modem interface are sensed:
0
RD Received
Data (Polarity
1S
inverted)
0
CTS
Clear
to
Send
0
DSR
Data Set Ready
0 SRL
Secondary Received Line Signal
De tee tor
0
RLS
Received Line Signal Detector
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