______________
G: Ground (output pins are not tested)
H: Output logic High (VOH)
L: Output logic Low (VOL)
C: Clock pin
1: Input logic High (VIH)
0: Input logic Low (VIL)
<PgUp>: Page up
<PgDn>: Page down
<TAB>: Skip to the next field
Note that the voltage is TTL voltage.
11.3.3 Delete Pattern
Highlight the test pattern you wish to delete and click on OK button. A message box that is ‘Delete pattern.’
will display. By clicking OK button, the test pattern will be deleted and you can return to the main menu, &
also make sure that you have made the right selection. The only way to retrieve a deleted test pattern is to
recreate a pattern.
11.4 Self-Test
This option performs a self-test on the system hardware.
Warning:
Tianjin Weilei Techonlogy Ltd.
www.weilei.com TEL:022-83945122
FAX:022-83945121 2018-03-08