Xilinx Kintex-7 FPGA KC705 User Manual

20 www.xilinx.com KC705 Getting Started Guide
UG883 (v4.0.1) May 28, 2014
Advanced Bring-up Using the Base Targeted Reference Design
Components
The Kintex-7 FPGA Base TRD features these components:
• Kintex-7 FPGA integrated Endpoint block for PCI Express:
• Configured with 4 lanes at a 5 Gb/s link rate (Gen2) or 8 lanes at a 2.5 Gb/s link
rate (Gen1) for PCI Express v2.0
• Provides a user interface compliant with AXI4-Stream interface protocol
• Performance monitor tracks the integrated block’s AXI4-Stream interface for PCIe
transactions
• Bus Mastering Scatter-Gather Packet DMA from Northwest Logic, a multichannel
DMA:
• Supports full-duplex operation with independent transmit and receive paths
• Provides an AXI4-Stream interface on the back end
• Monitors the performance of data transfers in receive and transmit directions
• Provides an AXI4 memory-mapped target interface to access user-defined
registers
Note:
The Northwest Logic Packet DMA shipped with the Base TRD is an evaluation version
and expires after 12 hours of run time. To get the full version, contact Northwest Logic [Ref 7].
• Multiport Virtual FIFO:
• DDR3 SDRAM SODIMM (64-bit @ 1600 Mb/s; 800 MHz) is used for buffering
packets. The memory controller delivered through the memory interface
generator (MIG) tool interfaces to the DDR3 memory.
• AXI Interconnect IP along with the memory controller supports multiple ports on
the memory.
• The Packetized Virtual FIFO controller controls addressing of the DDR3 memory
for each port, allowing DDR3 to be used as Virtual Packet FIFO.
• Software driver for a 32-bit Linux platform:
• Configures the hardware design parameters
• Generates and consumes traffic
• Provides a GUI to report status and performance statistics
The Kintex-7 FPGA integrated Endpoint block for PCI Express and the Packet DMA are
responsible for data transfers from host system to Endpoint card (S2C) and Endpoint card
to host system (C2S). Data to and from the host is stored in a Virtual FIFO built around the
DDR3 memory. This Multiport Virtual FIFO abstraction layer around the DDR3 memory
allows the user to move traffic efficiently without the need to manage addressing and
arbitration on the memory interface. It also provides more depth than storage
implemented using Block RAMs.
The integrated Endpoint block for PCI Express, Packet DMA, and Multiport Virtual FIFO
form the base system. The base system can bridge the host to any user application running
on the other end. The raw data packet module is a dummy application that generates and
consumes packets. It can be replaced by any user specific protocol like Aurora or XAUI.
The software driver runs on the host system. It generates raw data traffic for transmit
operations in the S2C direction. It also consumes the data looped back or generated at the
application end in the C2S direction.
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Xilinx Kintex-7 FPGA KC705 Specifications

General

FPGA Speed Grade	-2
FPGA Package	FFG900
Logic Cells	326, 080
DSP Slices	840
Clock Management Tiles	10
Transceivers	16
DDR3 Memory	1GB
Flash Memory	128MB
Clock	200 MHz oscillator
Form Factor	ATX
Ethernet	10/100/1000
Expansion Connectors	FMC
USB	USB-UART