Xilinx Kintex-7 FPGA KC705 User Manual

KC705 Getting Started Guide www.xilinx.com 31
UG883 (v4.0.1) May 28, 2014
Advanced Bring-up Using the Base Targeted Reference Design
3. Verify TRD operations through the status information provided by the GUI (see
Figure 21).
a. Verify the PCIe throughput.
b. Verify the DMA channel throughput for the Raw Data Path0.
c. Verify the DMA channel throughput for the Raw Data Path1.
d. Verify there are no buffer descriptor errors for error-free operation.
X-Ref Target - Figure 20
Figure 20: Start Data Traffic from the Performance Monitor
UG883_20_121112
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Xilinx Kintex-7 FPGA KC705 Specifications

General

FPGA Speed Grade	-2
FPGA Package	FFG900
Logic Cells	326, 080
DSP Slices	840
Clock Management Tiles	10
Transceivers	16
DDR3 Memory	1GB
Flash Memory	128MB
Clock	200 MHz oscillator
Form Factor	ATX
Ethernet	10/100/1000
Expansion Connectors	FMC
USB	USB-UART