Xilinx Kria K26 SOM - Page 33

MIO Bank 501 – PMU MIO Considerations
The Zynq UltraScale+ MPSoC plaorm management unit (PMU) processor has access to a subset of the MIO in bank 501 that are also
available to the clock-capable I/O and should be given special consideraon for the implementaon of power-down and power control
funconality of the SOM and carrier card design. The SOM power management reserved pins MIO32–34 and are idened in green.
There are also two pins related to oponal PMU features made available in the SOM PMU reference implementaon that implements
an external shutdown request and can control an external plaorm watchdog funcon. These MIO501 oponal feature pins are shown
in orange.
• External shutdown request: MIO31 – PMU input pin
• External watchdog toggle: MIO35 – PMU output pin
MIO Bank 501 – UART
RECOMMENDED: The carrier card design should include a UART for board bring-up and inial debug. The Xilinx K26 boot rmware and PetaLinux
BSP default the UART interface to MIO36 and MIO37. It is recommended that carrier card designs use this same mapping to be able to use the Xilinx
provided soware references.
Bank 501 MIO # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Peripheral PMU_GPI PMU_GPO PMU_GPO PMU_GPO PMU_GPO UART1
Pin Fct shtdwn_req FPD_Pwr_En PL_Pwr_EN PS_Pwr_En WD_out txd rxd
MIO Bank 502
MIO bank 502 has no pin reservaons relave to the carrier card design, beyond those dened in Zynq UltraScale+ Device Technical
Reference Manual (UG1085).
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 33
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