Xilinx Kria K26 SOM - Configuration and Control Signals

Table 7: K26 SOM PCB Signal Delays by I/O Bank
I/O Bank Minimum Delay (Inches) Maximum Delay (Inches)
MIO bank 501 1.53 2.02
MIO bank 502 1.36 2.05
HDA 1.48 2.05
HDB 1.74 2.02
HDC 1.72 2.49
HPA 1.49 1.89
HPB 2.13 2.87
HPC 1.21 2.04
SOM I/O Drive Strength Definition
For up to eight inches of trace length on the carrier card, the recommendaon is to use a 4 mA
drive strength and a slow slew rate for all MIO and HDIO signals. When trace lengths on the
carrier card are longer than eight inches, signal integrity simulaons might be necessary to select
the correct drive strength and proper terminaon.
RECOMMENDED: For MIO signals that are local to the SOM on MIO bank 500 and part of MIO bank
501, the recommendaon is to use a 4 mA drive strength and slow slew rate.
For I/O modeling, including drive strength sengs, the Zynq UltraScale+ MPSoC IBIS models can
be downloaded from the Xilinx website.
SOM Configuration and Control Signals
This secon outlines the conguraon and control signals associated with managing the Zynq
UltraScale+ MPSoC SOM.
Power-on Reset (PS_POR_B) Signal
This is the Zynq UltraScale+ MPSoC power-on reset signal. In Xilinx documentaon this signal is
also described as PS_POR_B. The POR_B signal is an acve-Low signal that must be asserted
during the SOM power-up sequence.
System Reset (PS_SRST_B) Signal
This system reset is primarily used for debug acvies and is funconally equivalent to POR_B
except for clearing a subset of PS power-on and error registers. See the Zynq UltraScale+ Device
Technical Reference Manual (UG1085) for more informaon.
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 28
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