Xilinx Kria K26 SOM - I;O Constraints and Drive Strength

GTH Transceivers
GTH transceivers support a maximum transfer rate of 12.5 Gb/s over each lane.
• To minimize the impedance disconnuity at the SOM connector interface, route the GTH
signals using a 90Ω dierenal impedance.
• Match P and N dierenal signals to within ±0.5 mils of each other.
• Route GTH signals in internal roung layers as a stripline structure.
• Route GTH signals with a maximum of two via transions. Ensure adequate ground return vias
are placed next to the signal vias to minimize crosstalk.
• Route GTH signals to have a maximum via stub length of less than 24 mils. It is a good design
pracce to minimize the stub length to avoid reecons.
• GTH dierenal signals to all other signal spacing should be ve mes the distance between
the signal to the nearest GND plane.
Reference Clocks
Both the PS-GTR and PL-GTH transceivers dierenal clock signals (REFCLKs) must meet
following signal integrity requirements.
• The target dierenal impedance of 100Ω.
• Match P and N dierenal signals to within ±0.5 mils of each other.
• REFCLK to all other signal spacing should be ve mes the distance between the signal to the
nearest GND plane.
I/O Constraints Definition
SOM I/O Timing Model
When creang an I/O ming model, you should include the Zynq
®
UltraScale+™ MPSoC package
and K26 SOM PCB signal delays for all MIO, HDIO, and HPIO related interfaces.
TIP:
The K26 SOM device and package delay le is available in the Vivado
®
tools.
The following table denes the physical length associated with each I/O bank from the Zynq
UltraScale+ MPSoC to the corresponding board-to-board connector.
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 27
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