Xilinx Kria K26 SOM - Page 29

BOOT_MODE Signals
The BOOT_MODE pins dene the physical device that the Zynq UltraScale+ MPSoCwill read
boot rmware from. The boot rmware is prepackaged as a boot.bin, which is a consolidated
boot rmware binary constructed using the Xilinx Bootgen tool outlined in the Bootgen User
Guide (UG1283).
The SOM includes two non-volale storage devices: QSPI and eMMC. The BOOT_MODE
strapping denes the primary boot device. Alternave boot devices can be designed on your
carrier card via MIO banks 501 and 502. The BOOT_MODE memory device selecon resistor
strapping is dened in the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
JTAG Port Interfaces
The JTAG interface uses a serial conguraon mode, popular for prototyping and board test. The
four-pin JTAG interface consisng of pins TMS, TDO, TDI, and TCK is included for debug
purposes and recommended to be accessible through the carrier card, regardless of boot mode
selected. For more informaon, see the JTAG Interface secon in Zynq UltraScale+ Device
Technical Reference Manual (UG1085).
PS_ERROR_OUT Signal, PS_ERROR_STATUS Commands
PS_ERROR_OUT is asserted when there is an accidental loss of power, a hardware error, or an
excepon in the PMU. For secure scenarios where device status is disabled from external
visibility, there are PMU control registers to mask PS_ERROR_OUT. For more informaon, see
the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
PS_ERROR_STATUS indicates a secure lockdown state. Alternavely, it can be used by the PMU
rmware to indicate system status. For secure scenarios where device status is disabled from
external visibility, there are PMU control registers to mask PS_ERROR_STATUS. For more
informaon, see the Zynq UltraScale+ Device Technical Reference Manual (UG1085).
Power Management Unit (PMU)
The PMU processor of the Zynq UltraScale+ MPSoC has access to a subset of the I/O in bank
501 that should be given special consideraon during the implementaon of power-down and
power control funconality in the SOM and carrier card design. The PMU applicaon can be
customized by the carrier card designer. However, the Xilinx PMU reference implementaon uses
the following pin mappings:
• HW Requested Shutdown: MIO31 is the SOM input signal
• External Watchdog Trigger: MIO35 is the SOM output signal
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 29
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