Xilinx Kria K26 SOM - Page 30

Sideband Signals
The sideband signals consist of power, processor, and conguraon signals. V
CCO
for sideband
signals is 1.80V.
• JTAG: The JTAG signals JTAG_TCK_C2M, JTAG_TMS_C2M, JTAG_TDI_C2M, and
JTAG_TDO_M2C connect to the SOM Zynq UltraScale+ MPSoC JTAG port.
• I2C: The I2C signals I2C_SCK and I2C_SDA connect to an I2C master on MIO bank 500 of the
SOM Zynq UltraScale+ MPSoC. The I2C I/O standard is 1.8V.
• PS_MODE[3:0]: The connector PS_MODE[3:0] pins connect to the SOM Zynq UltraScale+
MPSoC PS_MODE pins. All mode pins are pulled High to 1.8V through a resistor on the
SOM.The carrier card boot mode is required to set the PS_MODE pins to a valid boot mode as
dened in the Zynq UltraScale+ Device Technical Reference Manual (UG1085). To congure a
PS_MODE pin to a logic 1, the pin must be le oang, to congure a logic 0, the PS_MODE
pin must be connected to GND with a 0Ω resistor.
• PS_POR_L: During power up, a voltage monitor keeps PS_POB_L asserted (Low) unl all SOM
power rails are stabilized. Aerward, PS_POR_L is released and the boot process starts. A
carrier card can use PS_POR_L to reset any on-board devices. The carrier card can also force
PS_POR_L Low to extend the reset during power on to reset the system at any me.
• PS_SRST_C2M_L: The PS_SRST_C2M_L pin connects to PS_SRST_B signal on the SOM Zynq
UltraScale+ MPSoC. PS_SRST_B input signal to the Zynq UltraScale+ MPSoC is the system
reset signal, and it is commonly used during debug. PS_SRST_C2M_L is pulled High to 1.8V on
the SOM.
Power Management Signals
• PWROFF_ C2M_L:
• PWROFF_C2M_L is an acve-Low signal to power down the SOM and pulled High to the
+5V SOM input power rail.
• When PWROFF_C2M_L is asserted, the SOM power regulators perform a full-power
shutdown of the device following the correct regulator power-down sequence. This signal
does not alert applicaon soware to the power shutdown.
• Upon deasseron of PWROFF_C2M_L, the SOM power regulators iniate a power-on
sequence.
Note: Asserng PWROFF_C2M_L does not perform a soware shutdown or nofy the system of the
shutdown. The power regulators will start to power down instantly. Use the MIO31_SHUTDOWN pin
and PMU funconality to iniate a soware shutdown.
• PWRGD_LPD_M2C: PWRGD_LPD_M2C is an acve-High output signal from the SOM power
system that indicates the power status of all SOM PS low-power domain (LPD) rails.
PWRGD_LPD_M2C is pulled High to 1.80V on the SOM. A carrier card can use this signal to
monitor LPD status.
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 30
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