Xilinx Kria K26 SOM - Page 36

Voltage Rail Monitoring
A subset of the SOM rails can be monitored using the system monitor (SYSMON) available on
the Zynq UltraScale+ MPSoC. For more informaon on the SYSMON, see UltraScale Architecture
System Monitor User Guide (UG580).
Table 10: Voltage Rail Domains
Domain SYSMON on Zynq UltraScale+ MPSoC Power Rail on SOM
+5V Input V
P
/V
N
V
IN_5V0
PS V
CC_PSINTLP
V
CC_PSINTFP
V
CC_PS_0V85
(0.85V)
PS V
CC_PSAUX
V
CC_PS_1V80
(1.8V)
PL V
CCINT
V
CC_PL_0V72
(0.72V)
PL V
CCAUX
V
CC_PL_1V80
(1.8V)
PL V
CCBRAM
V
CC_PL_0V85
(0.85V)
The Zynq UltraScale+ MPSoC SYSMON is supported for Linux applicaons by the Xilinx analog
mixed signal (AMS) driver, available in the Xilinx ADC GitHub. The SYSMON is supported for
bare-metal applicaons by the SYSMONPSU driver.
SOM Power Integrity
The K26 SOM is equipped with adequate decoupling capacitors on all PS and PL voltage rails to
support a dened set of transient step loads. The programmable logic (PL) and processing system
(PS) designs must not exceed the specied maximum current limit and the corresponding step
loads as listed in the following tables.
Table 11: PL Design Limits
Voltage Rail Voltage (V)
Maximum Current
(A)
Step Load (% of Maximum Current)
V
CCINT
0.72 6.5 50
V
CCINT_VCU
0.9 3.5 50
Table 12: PS Design Limits
Voltage Rail Voltage (V)
Maximum Current
(A)
Step Load (% of Maximum Current)
V
CC_PSINTLP
and
V
CC_PSINTFP
0.85 3.5 25
V
CCO_PSIO
1.8 0.300 100
Chapter 2: Electrical Design Considerations
UG1091 (v1.0) April 20, 2021 www.xilinx.com
Carrier Card Design for Kria SOM 36
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