Xilinx VC707 - Page 88

88 www.xilinx.com VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
Appendix C: Master Constraints File Listing
set_property PACKAGE_PIN AD3 [get_ports PCIE_RX4_N]
set_property PACKAGE_PIN AH4 [get_ports PCIE_TX5_P]
set_property PACKAGE_PIN AE6 [get_ports PCIE_RX5_P]
set_property PACKAGE_PIN AH3 [get_ports PCIE_TX5_N]
set_property PACKAGE_PIN AE5 [get_ports PCIE_RX5_N]
set_property PACKAGE_PIN AJ2 [get_ports PCIE_TX6_P]
set_property PACKAGE_PIN AF4 [get_ports PCIE_RX6_P]
set_property PACKAGE_PIN AJ1 [get_ports PCIE_TX6_N]
set_property PACKAGE_PIN AF3 [get_ports PCIE_RX6_N]
set_property PACKAGE_PIN AK4 [get_ports PCIE_TX7_P]
set_property PACKAGE_PIN AG6 [get_ports PCIE_RX7_P]
set_property PACKAGE_PIN AK3 [get_ports PCIE_TX7_N]
set_property PACKAGE_PIN AG5 [get_ports PCIE_RX7_N]
set_property PACKAGE_PIN W2 [get_ports PCIE_TX0_P]
set_property PACKAGE_PIN Y4 [get_ports PCIE_RX0_P]
set_property PACKAGE_PIN W1 [get_ports PCIE_TX0_N]
set_property PACKAGE_PIN Y3 [get_ports PCIE_RX0_N]
set_property PACKAGE_PIN AA2 [get_ports PCIE_TX1_P]
set_property PACKAGE_PIN AA6 [get_ports PCIE_RX1_P]
set_property PACKAGE_PIN AA1 [get_ports PCIE_TX1_N]
set_property PACKAGE_PIN AA5 [get_ports PCIE_RX1_N]
set_property PACKAGE_PIN AB7 [get_ports PCIE_CLK_QO_N]
set_property PACKAGE_PIN AB8 [get_ports PCIE_CLK_QO_P]
set_property PACKAGE_PIN AC2 [get_ports PCIE_TX2_P]
set_property PACKAGE_PIN AB4 [get_ports PCIE_RX2_P]
set_property PACKAGE_PIN AC1 [get_ports PCIE_TX2_N]
set_property PACKAGE_PIN AB3 [get_ports PCIE_RX2_N]
set_property PACKAGE_PIN AE2 [get_ports PCIE_TX3_P]
set_property PACKAGE_PIN AC6 [get_ports PCIE_RX3_P]
set_property PACKAGE_PIN AE1 [get_ports PCIE_TX3_N]
set_property PACKAGE_PIN AC5 [get_ports PCIE_RX3_N]
#USR CLOCKS
set_property PACKAGE_PIN AU34 [get_ports SI5324_INT_ALM_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SI5324_INT_ALM_LS]
set_property PACKAGE_PIN AT36 [get_ports SI5324_RST_LS]
set_property IOSTANDARD LVCMOS18 [get_ports SI5324_RST_LS]
set_property PACKAGE_PIN AD8 [get_ports SI5324_OUT_C_P]
set_property PACKAGE_PIN AD7 [get_ports SI5324_OUT_C_N]
set_property PACKAGE_PIN E19 [get_ports SYSCLK_P]
set_property IOSTANDARD LVDS [get_ports SYSCLK_P]
set_property PACKAGE_PIN E18 [get_ports SYSCLK_N]
set_property IOSTANDARD LVDS [get_ports SYSCLK_N]
set_property PACKAGE_PIN AW32 [get_ports REC_CLOCK_C_P]
set_property IOSTANDARD LVCMOS18 [get_ports REC_CLOCK_C_P]
set_property PACKAGE_PIN AW33 [get_ports REC_CLOCK_C_N]
set_property IOSTANDARD LVCMOS18 [get_ports REC_CLOCK_C_N]
#MGTs
set_property PACKAGE_PIN AK7 [get_ports SMA_MGT_REFCLK_N]
set_property PACKAGE_PIN AK8 [get_ports SMA_MGT_REFCLK_P]
set_property PACKAGE_PIN AP4 [get_ports SMA_MGT_TX_P]
set_property PACKAGE_PIN AN6 [get_ports SMA_MGT_RX_P]
set_property PACKAGE_PIN AP3 [get_ports SMA_MGT_TX_N]
set_property PACKAGE_PIN AN5 [get_ports SMA_MGT_RX_N]
set_property PACKAGE_PIN E10 [get_ports FMC1_HPC_GBTCLK1_M2C_C_P]
set_property PACKAGE_PIN E9 [get_ports FMC1_HPC_GBTCLK1_M2C_C_N]
set_property PACKAGE_PIN A10 [get_ports FMC1_HPC_GBTCLK0_M2C_C_P]
set_property PACKAGE_PIN A9 [get_ports FMC1_HPC_GBTCLK0_M2C_C_N]
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