Xilinx ZCU104 - Uart0 (Mio 18-19)

ZCU104 Board User Guide 53
UG1267 (v1.1) October 9, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
The nets of the three UART channel are level-shifted by U161. The UART connections from
XCZU7EV MPSoC U1 PL-side bank 28 to the FT4232HL device through U161 are listed in
Table 3-18.
UART0 (MIO 18-19)
This is the primary Zynq UltraScale+ MPSoC PS-side UART interface and is connected to the
U151 FT4232HL USB-to-Quad-UART with port assignments as listed in Table 3-19. PS-side
UART0 is accessed through the U151 FT4232HL USB-to-Quad-UART bridge BDBUS port. The
UART connections from XCZU7EV MPSoC U1 PS-side MIO 18 and 19 to the FT4232HL device
through level-shifter U161 are listed in Table 3-19.
Table 3-18: XCZU7EV U1 PL-side to FT4232HL U151 Connections via L/S U161
XCZU7EV (U1) Pin Net Name
FT4232HL U151
Pin Name Pin #
A20 UART2_TXD_FPGA_RXD DDBUS1 52
C19 UART2_RXD_FPGA_TXD DDBUS0 48
C18 UART2_RTS_B DDBUS2 53
A19 UART2_CTS_B DDBUS3 54
Table 3-19: XCZU7EV U1 PS-side MIO 18, 19 to FT4232HL U151 Connections via L/S U161
XCZU7EG U1
Schematic Net Name
FT4232HL U151
Pin Name Pin# Pin Name Pin #
PS_MIO18 F27 UART0_TXD_MIO18_RXD BDBUS1 27
PS_MIO19 B28 UART0_RXD_MIO19_TXD BDBUS0 26
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