Xilinx ZCU104 User Manual

ZCU104 Board User Guide 55
UG1267 (v1.1) October 9, 2018 www.xilinx.com
Chapter 3: Board Component Descriptions
DPAUX (MIO 27-30)
[Figure 2-1, callout 27]
The Zynq UltraScale+ MPSoC provides a VESA DisplayPort 1.2 source-only controller that
supports up to two lanes of main link data at rates of 1.62 Gb/s, 2.70 Gb/s, or 5.40 Gb/s. The
DisplayPort standard defines an auxiliary channel that uses LVDS signaling at a 1 Mb/s data
rate, which is translated from single-ended MIO signals to the differential DisplayPort AUX
channel, DPAUX (see Table 3-21). The DisplayPort circuit is shown in Figure 3-15.
Table 3-21: DPAUX/MIO Connections
XCZU7EV (U1) Pin Net Name
Level Shifter U114
Pin Name Pin #
A33 MIO30_DP_AUX_IN 2A1 8
A32 MIO29_DP_OE 1A2 7
A31 MIO28_DP_HPD 2A2 9
A30 MIO27_DP_AUX_OUT 1A1 6
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Xilinx ZCU104 Specifications

General

Brand	Xilinx
Model	ZCU104
Category	Motherboard
Language	English