Zynq UltraScale+ VCU TRD User Guide 73
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
Tab le 5 -2 shows the address map of various IP blocks used in the PL of an audio design.
HDMI 1.4/2.0 Transmitter Subsystem v2.0 0x00A0020000 128K
Video Mixer 0x00A0070000 64K
Video Processing Subsystem (VPSS) 0x00A0080000 256K
Video Processing Subsystem (VPSS-CSC) 0x00A0240000 64K
Video Processing Subsystem (VPSS-Scaler) 0x00A0200000 256K
Video Timing Controller 0x00A00D0000 64K
Video Test Pattern Generator (TPG) 0x00A00E0000 64K
H.264/H.265 Video Codec Unit (VCU) 0x00A0100000 1M
Video PHY Controller 0x00A0060000 64K
Video Scene Change 0x00A02E0000 64K
Table 5-2: Address Map for Audio Design IP Blocks
IP Core Base Address Offset
Audio Clock Recovery 0x00_A029_0000 64K
Audio Formatter1 0x00_A005_2000 4K
Audio Formatter2 0x00_A005_1000 4K
AXI GPIO 0x00_A005_3000 4K
AXI Interrupt Controller 0x00_A005_5000 4K
HDMI ACR Control 0x00_A005_6000 4K
S_AXI 0x00_A005_0000 4K
I2S receiver 0x00_A00C_0000 64K
I2S transmitter 0x00_A00D_0000 64K
MIPI CSI-2 Receiver Subsystem 0x00_A00F_0000 64K
Sensor I2C Controller 0x00_A005_4000 4K
Sensor Demosaic 0x00_A025_0000 64K
HDMI Frame Buffer Read 0x00_A004_0000 64K
HDMI Frame Buffer Write 0x00_A001_0000 64K
MIPI Frame Buffer Write 0x00_A026_0000 64K
Gamma LUT 0x00_A027_0000 64K
HDMI Receiver subsystem 0x00_A000_0000 64K
HDMI Transmitter subsystem 0x00_A002_0000 128K
Video Mixer 0x00_A007_0000 64K
Video Processing Subsystem (VPSS) 0x00_A008_0000 256K
Video Processing Subsystem (VPSS-CSC) 0x00_A024_0000 64K
Table 5-1: Address Map for IP Blocks of the VCU TRD Full-fledged Design (Cont’d)
IP Core Base Address Offset