Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 75
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 5: Hardware Platform
Tab le 5 -5 shows the address map of various IP blocks used in the PL of an HDMI DDR
design.
Video Processing Subsystem (VPSS) 0x00_A008_0000 256K
SDI Receiver Subsystem 0x00_A003_0000 64K
SDI Transmitter Subsystem 0x00_A004_0000 128K
SDI audio embed 0x00_A001_0000 64K
SDI audio extract 0x00_A002_0000 64K
H.264/H.265 Video Codec Unit (VCU) 0x00_A010_0000 1M
VCU DDR4 Controller 0x00_B002_0000 64K
Table 5-5: Address Map for HDMI DDR Design IP Blocks
IP Core Base Address Offset
HDMI I2C Controller 0x00_A005_0000 4K
Sensor I2C Controller 0x00_A005_1000 4K
HDMI frame buffer read 0x00_A004_0000 64K
Video frame buffer read 0x00_A00F_0000 64K
HDMI frame buffer write 0 0x00_A001_0000 64K
TPG frame buffer write 0x00_A00C_0000 64K
Video frame buffer write 0x00_A020_0000 64K
HDMI frame buffer write 1 0x00_A02B_0000 64K
HDMI frame buffer write 2 0x00_A02C_0000 64K
HDMI frame buffer write 3 0x00_A021_0000 64K
HDMI Receiver subsystem 0x00_A000_0000 64K
HDMI Transmitter subsystem 0x00_A002_0000 128K
Video Mixer 0x00_A007_0000 64K
Video Processing Subsystem (VPSS) 0x00_A008_0000 256K
Video Timing Controller 0x00_A00D_0000 64K
Video Test Pattern Generator (TPG) 0x00_A00E_0000 64K
H.264/H.265 Video Codec Unit (VCU) 0x00_A010_0000 1M
VCU DDR4 Controller 0x48_0000_0000 2G
Video PHY Controller 0x00_A006_0000 64K
Table 5-4: Address Map for SDI Design IP Blocks (Cont’d)
IP Core Base Address Offset
Send Feedback

Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C