Xilinx Zynq UltraScale+ User Manual

Zynq UltraScale+ VCU TRD User Guide 9
UG1250 (v2019.1) May 29, 2019 www.xilinx.com
Chapter 1: Introduction
Figure 1-2 shows the software state after the boot process has completed and the
individual applications have been started on the target processing units. The TRD does not
use virtualization and therefore does not run a hypervisor on the APU.
The APU application controls the following video data paths implemented in the PS and PL
(see Figure 1-3, page 11):
• Capture pipeline capturing video frames into DDR memory from a high definition
media interface (HDMI source connected through the PL, an image sensor on an FMC
daughter card connected via MIPI CSI-2 RX Subsystem through the PL, serial digital
interface (SDI) source connected through the PL, and a Test Pattern Generator (TPG)
implemented inside the PL. Additionally, video can be sourced from a SATA drive, USB
3.0 device, or an SD card, which is also used as a boot device.
• Processing (memory-to-memory) pipeline includes VCU encode/decode. Video frames
are read from DDR memory, processed by the VCU, and written back to memory.
• Display pipeline reading video frames from memory and sending them to a monitor via
the DisplayPort TX Controller inside the PS, SDI Transmitter Subsystem through the PL
or the HDMI Transmitter Subsystem through the PL. The DisplayPort TX Controller
supports two layers—one for video, the other for graphics and the SDI Transmitter
Subsystem with mixer IP support up to four layers and HDMI Transmitter Subsystem
with mixer IP supports up to eight such layers.
The graphics layer is rendered by the GPU .
• Audio Capture pipeline to capture audio frames from HDMI-RX, SDI-RX and I2S-RX
interfaces.
X-Ref Target - Figure 1-2
Figure 1-2: Key Reference Design Components
ARM Cortex-A53-0
ApplicationOSProcessorPL
VCU_APM_LIB
VCU_GST_LIB
VCU_VIDEO_LIB
PCIe_LIB
VCU_GST_APP
VCU_QT
PCIe_TRANSCODE
ALSA
V4L2
DRM
pcie_ep_client
MEDIA
DMABUF
U10
ARM Cortex-A53-1
ARM Cortex-A53-2
ARM Cortex-A53-3
DisplayPort
GPU
USB
SATA
SD
TPG
HDMI-Tx
HDMI-Rx
CSI-Rx
VCU
PL DDR
SDI-Rx
SDI-Tx
PCIe
XDMA
I2S-Rx
I2S-Tx
SCD
X22060-041719
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Xilinx Zynq UltraScale+ Specifications

General

Manufacturer	Xilinx
Model	Zynq UltraScale+
Category	SoC
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
FPGA Fabric	UltraScale+ FPGA
Memory Interfaces	DDR4, DDR3, LPDDR3, LPDDR4
Connectivity	Gigabit Ethernet, USB 3.0, SATA, PCIe
Video Codecs	H.264
Power Consumption	Varies depending on specific device configuration and usage
Operating Temperature	Commercial: 0°C to +85°C, Industrial: -40°C to +100°C