YASKAWA CIMR-ACA4011 - Page 261

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PID Control Block
The following diagram shows the PID control block in the MxC.
Fig 6.63 PID Control Block
Option Card
Serial Com
Terminal A1
d1-01 d1-02 d1-16
Terminal A2 or A3 PID target value
MEMOBUS communications register 06 H PID target value
Frequency reference terminal A3 PID feedback
Z
-1
b5-03
+ −
+
P
b1-01
0 1 2
3,4
Frequency reference using multi-step command
PID Input Volume (U1-36)
Set PID target value in multi-function analog input
Set bit 1 of MEMOBUS register 0FH to 1
b5-01=2,4
b5-01=1,3
Proportional gain (P) b5-02
+
−
+
b5-17
-1
Select multi-function inputs PID input characteristics
PID SFS Cancel
H3-05 or H3-09=B
Output frequency
1 T
b5-05
− T
1
-1
PID Output Gain (b5-10)
Z
-1
Z
-1
Frequency reference (U1-01)
PID command (U1-38)
Integral (I) time
b5-03
Store integral using multi-function inputs
I limit
b5-01=1,3
b5-01=2,4
Derivative time
Integral reset using multi-function inputs
PID limit b5-06
PID Limit
PID Primary Delay Time Constant
b5-08
PID Offset Adjustment (b5-07)
Select PID Output Level Selection (b5-09)
+
+
−
+
+
+
+
−
+
+
+
+
PID Output Monitor (U1-37)
b5-01=0
b5-01=3,4
b5-01=1,2
PID ON
PID OFF
Multi-function input PID control cancel signal is on. PID is off under the following conditions: b5-01 = 0 During JDG command input
b5-11=0
b5-11=1
Enable/disable reverse operation when PI output is negative
Upper limit Fmax x109%
Lower limit 0
Uppwer limit
Fmax x109%
Lower limit
-(Fmaxx109%)
+
+
0
+
1
1
Z
-1