YOKOGAWA DLM3054 User Manual

4-64
IM DLM3054-01EN
Trigger Point
For all formats, in all modes, the trigger point is the stop bit after the trigger condition is met. If multiple data
frames are specified, the trigger point is the stop bit of the last data byte.
Data
7 bits (b0 to b6)
8 bits (b0 to b7)
Parity
Bit
Stop
Bit
Start
Bit
No parity bit for
NonParity
(Positive logic)
Triggers here
I
2
C Bus Trigger [ENHANCED, option]
The instrument triggers based on the I
2
C bus signal’s start condition or the address pattern or data pattern
trigger conditions. The following figure shows the I
2
C bus signal data format.
...
...
SDA
SCL
Start condition
1 2 3 4 5 6 7 8 9
Acknowledge bit
Data byte
1 2 3 4 5 6 7 8 9
Stop condition
Address + R/W bit
6 7 8 9
Serial Clock (SCL), Serial Data (SDA)
Source (Source)
Set the SCL and SDA source from one of the settings below. If you set the source to LOGIC, set the source bit (Bit0
to Bit7) and level.
CH1 to CH4, LOGIC (Bit 0 to Bit 7)
Level (Level), HF Rejection (HF Rejection), Noise Rejection (Noise Rejection)*
Set these items for the SCL and SDA sources.
These items are the same as those of the edge trigger.*
* You can set this only when the trigger source is set to LOGIC and the 701989 logic probe is connected.
Hysteresis (Hysteresis)
You can set this only when the trigger source is CH1 to CH4.
This item is the same as that of the CAN bus trigger.
Trigger Mode (Mode)
Select I
2
C bus trigger mode from one of the settings below.
Every Start: Triggers on start or restart condition
Address Date: Triggers on the AND of address pattern and data pattern conditions
NON ACK: Triggers when the acknowledge bit is Nack (SDA is H)
General Call: Triggers on general call addresses
Start Byte: Triggers on the start byte master code
HS Mode: Triggers on the HS Mode master code
4 Triggering

YOKOGAWA DLM3054 Specifications

General

Brand	YOKOGAWA
Model	DLM3054
Category	Test Equipment
Language	English