Motherboard Technical Specification
Page 28
default settings are 3CL.
Bank Interleave
Set this option to Enabled to enable DRAM banks interleave logic. The settings are
Enabled or Disabled. The optimal and fail-safe default settings are Enabled.
DRAM Timing Control
This option is used set DRAM timing of the chipset. For user convenience the options
are specified as Normal, Medium, Fast and Turbo. The optimal and fail-safe default
settings are Normal.
DRAM Pipeline
This option is used to enable or disable DRAM read and write pipeline logic. The
settings are Enabled or Disabled. The optimal and fail-safe default settings are Enabled
and Disabled respectively.
CPU to PCI Write Buffer
This option is used to enable or disable CPU to PCI write buffer logic. The settings are
Enabled or Disabled. The optimal and fail-safe default settings are Enabled and
Disabled respectively.
PCI Dynamic Bursting
This option is used to enable or disable PCI dynamic bursting logic in the chipset. The
settings are Enabled or Disabled. The optimal and fail-safe default settings are Enabled
and Disabled respectively.
PCI Burst
This option is used to enable or disable PCI burst logic in the chipset. The settings are
Enabled or Disabled. The optimal and fail-safe default settings are Enabled and
Disabled respectively.
Quick Frame Generation
This option is used to enable or disable quick frame generation logic. The settings are
Enabled or Disabled. The optimal and fail-safe default settings are Enabled and
Disabled respectively.
PCI Master 1 WS Write
This option is used to enable or disable PCI master 1 wait state write logic in the
chipset. The settings are Enabled or Disabled. The optimal and fail-safe default settings
are Disabled.
PCI Peer Concurrency
This option is used to enable or disable PCI peer concurrency logic in the chipset. The
settings are Enabled or Disabled. The optimal and fail-safe default settings are
Disabled.
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