RFSoC Data Converter Evaluation Tool User Guide 60
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 9: System Considerations
provides advanced management features instead of the PMU ROM. It then loads the first
stage boot loader (FSBL) into OCM and, if enabled, switches into tamper monitoring mode.
In this design, the FSBL is executed on APU-0. It initializes the PS and configures the PL and
APU based on the boot image header information. The following steps are performed:
1. The PL is configured with a bitstream and the PL reset is deasserted.
2. The ARM trusted firmware (ATF) is loaded into OCM and executed on APU-0.
3. The second stage boot loader U-Boot is loaded into DDR to be executed by APU-0.
For more information on the boot process, see chapters Programming View of Zynq
UltraScale+ MPSoC Devices and System Boot and Configuration in the Zynq UltraScale+
MPSoC Software Developer Guide (UG1137) [Ref 11], and chapter Boot and Configuration in
the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3].
Global Address Map
For more information on system addresses, see the System Addresses chapter in the Zynq
UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3].
Memory
The DMA instances in the PL use a 36-bit address space so they can access the DDR Low and
DDR High address. Table 9-1 lists the APU software components used in this design and
where they are stored or executed from in memory.
Table 9-1: Software Executables and Their Memory Regions
Component Processing Unit Memory
FSBL APU-0 OCM
ARM trusted firmware (ATF) APU-0 OCM
U-Boot APU-0 DDR
Linux kernel/device tree/rootfs APU (SMP) DDR
rftool application (Linux) APU (SMP) DDR
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