Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 65
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Appendix A: Reference Design Protocol Specification
#invalid number of arguments
SetMixerSettings 0
Error: SetMixerSettings: Invalid Number of Arguments
# valid command and response (no data returned - args: Type, Tile, Block, Freq,
PhaseOffset, EventSource, FineMixerMode, CoarseMixerFreq, FineMixerScale)
SetMixerSettings 0 1 2 3.4 0.0 ..
SetMixerSettings:
#valid command and response (data returned - Freq, PhaseOffset, EventSource,
FineMixerMode, CoarseMixerFreq, FineMixerScale)
GetMixerSettings 0 1 2
GetMixerSettings: 3.14 ...
Control Path Core Implementation
Structure
The control path core code is implemented in C code and runs on the APU. The main
functions are separated into files so the protocol-core is independent from the interface
input or output and the commands themselves. This allows easier re-use and extension.
Files:
• io_interface (.c/.h)
°
This file contains the communication specific code that implements
getString/sendString
°
The sub-functions here are used to separate the core (cmd_interface) from the
physical communications channel.
°
To port to another communications medium, this is the only file that should be
edited.
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC