RFSoC Data Converter Evaluation Tool User Guide 27
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 4: Clocking
scheme allows the application software to program the PLL chip sets without any external
tools.
The LMK component shown in Figure 4-1 provides a low jitter and low noise clock to RFDC
IP and to RF PLLs which act as a source for further clock generation and clock
synchronization. LMK modules generate six clock outputs that are connected to these
various blocks and components:
•PL: Sys Ref
•DAC: Sys Ref
•PL: FPGA Ref Clk
•LMX: Ref Clock
•LMX: Sync Clock
• SMA: 12.8 MHz Clock
Refer to Appendix A, Reference Design Protocol Specification for more details about clock
commands and arguments.
In each Zynq UltraScale+ RFSoC, each RF-ADC or RF-DAC tile has its own clock input.
Additionally, there is a dedicated input PL SYSREF pin pair per package. The PL SYSREF clock
is used for multi-tile and multi-chip synchronization. For multi-tile designs, the PL SYSREF
connects into a master tile and the signal is distributed within the master tile and all the
other tiles in the design. The generation from PL SysRef is done using the output of the LMK
module. The RFDC IP requires PL SysRef synchronously captured in the PL. For this purpose,
PL SysRef provided to the IP must be synchronous to the clock domain of the group, i.e., PL
clock. This is achieved using the logic diagram shown in Figure 4-2.
X-Ref Target - Figure 4-2
Figure 4-2: SysRef Synchronization
Sync
1
st
Stage
PL SYSREF (LMK)
Sync
2
nd
Stage
MMCM
PL REF CLK (LMK) Fabric Clock
user_sysref to RFdc
Fabric Logic
X21245-092118
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