RFSoC Data Converter Evaluation Tool User Guide 54
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 7: Protocol Specification
At a high-level, all datapaths do the same function, i.e., writing and reading data to and
from memories. At a low-level, data is read and written to and from PS/PL DDR and DMA is
triggered to copy data to RFDC. Datapath supports two commands: writedatatomemory
and readdatafrommemory.
Using the writedatatomemory command, you can send data from a remote PC to the
RFSoC board via Ethernet. On receiving this command, the socket application reads data
over Ethernet and copies data to the PL-DDR. After data is copied to PL-DDR, DMA is
triggered to transfer data from PL-DDR to DAC.
Using the readdatafrommemory command, you can receive data from the RFSoC board
over Ethernet. On receiving this command, the socket application triggers DMA to transfer
data from ADC to PL-DDR. After data is available in the PL-DDR, the socket application
sends this data over Ethernet to a remote PC.
To support PL DDR mode, firmware checks the selected channels. Based on this information,
the firmware creates a bitmask for the selected channels and updates the hardware register,
so that the hardware knows the enabled channels.
Depending on the numbers of channels, invoke dmaengine_prep_dma_cyclic (dma_addr,
length) and dmaengine_submit() multiple times. These functions prepare the BD list in the
DMA driver. For each iteration, increment dma_addr by 128k for each channel, depending
on the size. For example, if the number of channels is 4 and the size of the channel is
128 MB, invoke the above two functions 4096 times. Invoke dma_async_issue_pending () to
start DMA.
Multi-Tile Sync
For details about the multi-tile sync feature, see the “Multi-Converter Synchronization” section of the
Zynq UltraScale+ RFSoC RF Data Converter LogiCORE IP Product Guide (PG269) [Ref 9].
DAC Flow for Non-MTS
1. This sequence needs to be followed for each writedatatomemory () command per
DAC channel:
a. Get Tile Id, Block ID, and size of data.
b. Get DAC memory pointer for the corresponding DAC channel.
c. Read data from the GUI.
d. Disable Channel X Control GPIO (X = 0…7) for corresponding DAC.
e. Select requested DAC channel by configuring streaming MUX GPIO.
f. Assert external FIFO RESET for corresponding DAC channel.
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