RFSoC Data Converter Evaluation Tool User Guide 55
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 7: Protocol Specification
g. Deassert external FIFO RESET for corresponding DAC channel.
h. Enable RFDC FIFO for corresponding DAC channel.
i. Trigger SG DMA.
j. On DMA completion, enable Channel X Control GPIO (X = 0…7) as per selected DAC.
DAC Flow for MTS
1. MTS_Setup (enable, DAC) command
k. Disables RFDC FIFOs for all eight channels (DAC0 to DAC7).
l. Asserts the external Memory Loopback Reset signal for all eight DAC pipelines
(DAC0 to DAC7).
m. Configures the Multi-Tile Control select signal to enable PL CLK out of BUFGMUX
and to enable Channel 0 Control (common channel control signal).
n. Deasserts external FIFO RESET signal for all eight DAC pipelines (DAC0 to DAC7).
o. Enables RFDC FIFOs for all eight channels.
2.
MultiConverter_Init (DAC) command
a. Triggers XRFdc_MultiConverter_Init() command and returns status. This is
an RFDC driver internal function.
3. MultiConverter_Sync (DAC, latency) command
a. Triggers XRFdc_MultiConverter_Sync () command and returns the status.
4. This sequence needs to be followed for each writedatatomemory() command per
DAC channel:
a. Get tile Id, block ID, and size of data.
b. Get DAC memory pointer for the corresponding DAC channel.
c. Read data from the GUI.
d. Select the requested DAC channel by configuring streaming MUX GPIO.
e. Trigger SG DMA (non-cyclic).
f. Wait for DMA completion. (Wait for DMA completion means that TLAST is asserted at
the input of the DAC path.)
g. LocalMemTrigger (DAC) command
a. Enable Channel 0 Control GPIO.
Note:
For information on how buffers are set up, see Memory Mapping for RF-DAC/RF-ADC.
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