RFSoC Data Converter Evaluation Tool User Guide 56
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 7: Protocol Specification
MTS Disable Flow for DAC
1. Send MTS_Setup (disable, DAC) command with disable argument.
a. Configure Multi-Tile Control select signal to enable Tile0_DAC_Clock and
Tile1_DAC_Clock out of BUFGMUX and to disable Channel 0 Control (common
channel control signal).
b. Disable channel control GPIOs (Channel 'X' Control) for all DACs (X = 0...7).
c. Disable RFDC FIFO for all DAC pipelines (DAC0 to DAC7).
DAC Flow for PL DDR
1. Select DDR mode.
2. Generate equal sizes of patterns while loading more than one (firmware tracks the
tile/block IDs and increments the channel count).
3. Write to the scratch pad register to route the BDs to the corresponding FIFOs of the DAC
channel.
4. The firmware prepares the BD chain and triggers the DMA transfer.
5. Send the Stop command to reset the
currently running DMA transfers (before selecting
any other mode or sending new data or selection of new channels in DDR mode).
ADC Flow for MTS
1. MTS_Setup (enable, ADC) command
a. Disable RFDC FIFOs for all eight channels (ADC0 to ADC7).
b. Assert external FIFO RESET signal for all eight DAC pipelines (ADC0 to ADC7).
c. Configure Multi-Tile Control select signal to enable PL CLK out of BUFGMUX and to
enable Channel 0 Control (common channel control signal).
d. Deassert external FIFO RESET signal for all eight DAC pipelines (ADC0 to ADC7).
e. Enable RFDC FIFOs for all eight channels.
2. MTS_init (ADC) command
a. Trigger XRFdc_MultiConverter_Init() command and return the status.
3. MTS_Sync (ADC, latency) command
a. Trigger XRFdc_MultiConverter_Sync() command and return the status.
4. LocalMemTrigger (ADC) command
a. Enable Channel 0 Control GPIO.
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