Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 57
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 7: Protocol Specification
5. This sequence needs to be followed for each readdatafrommemory () command per
ADC channel.
a. Get Tile Id, Block ID, and size of data.
b. Select requested ADC channel by configuring streaming MUX GPIO.
c. Enable IQ GPIO, if IQ mode is selected.
d. Trigger DMA.
e. Send requested ADC data to GUI.
ADC Flow for Non-MTS
This sequence needs to be followed for each readdatafrommemory() command per ADC
channel:
1. Get Tile Id, Block ID, and size of data.
2. Get ADC memory pointer for the corresponding channel.
3. Select requested ADC channel by configuring streaming MUX GPIO.
4. Enable IQ GPIO, if IQ mode is selected.
5. Assert external FIFO RESET for corresponding ADC channel.
6. Deassert external FIFO RESET for corresponding ADC channel.
7. Enable RFDC FIFO of corresponding ADC channel.
8. Enable Channel X Control GPIO (X = 0…7) as per selected ADC.
9. Trigger SG DMA.
10. Disable RFDC FIFO of the corresponding ADC channel.
11. Send requested ADC data to the GUI.
MTS Disable Flow for ADC
1. Send MTS_Setup (disable, ADC) command with the disable argument.
a. Configure Multi-Tile Control select signal to enable Tile0_ADC_Clock,
Tile1_ADC_Clock, Tile2_ADC_Clock, and Tile3_ADC_Clock, out of BUFGMUX and to
disable Channel 0 Control (common channel control signal).
b. Disable channel control GPIOs (Channel 'X' Control) for all ADCs.
c. Disable RFDC FIFO for all ADC pipelines (ADC0 to ADC7).
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC