Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 37
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 5: Evaluation Tool System Configuration using the GUI
External Component Configuration
In the overview tab, when clicking on Clock Settings, the external PLL can be configured
with a set of predefined frequencies as shown in Figure 5-1.
When clicking on Power Settings, the DAC power mode can be changed between 20 mA
and 32 mA.
X-Ref Target - Figure 5-1
Figure 5-1: Overview of External PLLs
X21283-090918
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC