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Zynq UltraScale+ - DAC Configuration Options; DAC Clock Configurations

Zynq UltraScale+
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RFSoC Data Converter Evaluation Tool User Guide 42
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 5: Evaluation Tool System Configuration using the GUI
Digital Down Converter Configurations
The GUI supports:
Setting up complex mixer functionality and NCO frequency
Setting the decimation rate on the decimation filters
Selecting and configuring the decimation filter in the PL, if desired
Configuring the quadrature modulator correction block
Enabling and configuring dual band support
DAC Configuration
Like the ADC tiles, the DAC tiles contain four DACs. Unlike the ADC tiles, there is only one
configuration. The DAC tile contains the same clock generation (PLL) functionality as the
ADC tiles and a digital up converter (DUC) signal processing block.
The following features are supported in the GUI:
DAC output current range (20 mA or 32 mA)
DAC low noise mode
DAC enhanced linearity mode
DAC mix mode operation for second Nyquist zone operation
DAC Clock Configurations
The GUI supports:
Selection of external or internal (PLL) sample clock options
On-chip PLL configuration for internal sample clock generation
Full access to configuring the on-chip PLLs using the software API
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