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General| Max Transceivers | Up to 32 |
|---|---|
| Transceiver Speed | Up to 32.75 Gbps |
| Family | Zynq UltraScale+ |
| Processor Cores | Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5 |
| Max Memory | DDR4 |
| Power Consumption | Varies by configuration, typically 10W to 30W |
| Operating Temperature | Industrial (-40°C to +100°C), Extended (-40°C to +125°C) |
| Package Options | Various BGA packages |
| Category | FPGA SoC |
Describes the Zynq UltraScale+ RFSoC family, its integrated subsystems, and key capabilities for radio applications.
Details the system-level block diagram, architecture, and components of the RF Data Converter evaluation tool.
Explains the Vivado IP integrator flow, hardware partitioning, and the overall hardware block diagram.
Details the datapath implementation for the 8-channel RF-DAC, including sample storage and replay methods.
Details the datapath implementation for the 8-channel RF-ADC, including IQ merge and channel selection.
Describes the clock domains, analog/mixed signal clocking structure, and PLLs used in the ZCU111 board.
Details support for multi-tile synchronization (MTS) and non-MTS modes, controlled by clock MUX.
Describes the different reset sources (PS, MIG) and their distribution to logic blocks and FIFOs.
Explains GUI configuration of external PLLs, including frequency settings and DAC power modes.
Details GUI support for configuring ADC tiles, including ADCs, DDCs, clock generators, and PLLs.
Describes GUI support for selecting and configuring external or internal sample clock options for ADCs.
Details GUI support for DAC configurations, including output current, linearity, and Nyquist zone operation.
Describes GUI support for selecting and configuring external or internal sample clock options for DACs.
Describes the software platform on the APU, the rftool application, and its interface to the GUI.
Explains the string-based, space-separated command and response protocol for GUI-Linux application communication.
Discusses the multi-tile synchronization feature for coordinated operation of multiple tiles.
Refers to the description of Linux APIs for the Zynq UltraScale+ RFSoC Data Converter.
Describes the non-secure boot flow and SD boot mode sequence, detailing component loading and execution.
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