Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 63
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Appendix A: Reference Design Protocol Specification
GetQMCSettings Type, Tile, Block Type, Tile, Block,
QMCSettings
Get QMC settings for the
requested type, tile, and block.
ShutDown Type, Tile None Shuts down a tile (the tile must be
enabled in the bitstream).
StartUp Type, Tile None Starts up a tile (the tile must be
enabled in the bitstream).
GetTileStatus Type, Tile TileStatus Returns the TileStatus returned
from an XRFdc_IPStatus function
call.
GetBlockStatus Type, Tile, Block BlockStatus SamplingFreq,
AnalogDataPathStatus,
DigitalDataPathStatus,
DataPathClocksStatus,
IsFIFOFlagsEnabled,
IsFIFOFlagsAsserted
GetPLLConfig Type, Tile RefClkFreq,
SampleRate,
RefClkDivider,
FeedbackDivider,
OutputDivider
Get PLL configuration for the
requested type and tile.
DynamicPLLConfig Type,Tile, Source,
Refclkfreq, sampling
rate
RefClkDivider,
FeedbackDivider,
OutputDivider
Configure the PLL sampling rate
depending on the source.
GetLinkCoupling Tile, Block Tile, Block, Mode Get link coupling mode for the
requested tile and block.
SetCoarseDelaySettings Type, Tile, Block Success/Fail Set Coarse delay settings for the
requested type, tile, and block.
GetCoarseDelaySettings Type, Tile, Block Type, Tile, Block,
CoarseDelay,
EventSource
Get coarse delay settings for the
requested type, tile, and block.
SetInterpolationFactor Tile, Block Success/Fail Set the interpolation factor for
the requested tile and block.
GetInterpolationFactor Tile, Block Tile, Block,
Interpolationfactor
Get interpolation factor for the
requested tile and block.
SetDecimationFactor Tile, Block Success/Fail Set decimation factor for the
requested tile and block.
GetDecimationFactor Tile, Block Tile, Block,
Decimationfactor
Get decimation factor for the
requested tile and block.
MultiConverter_Init Type Success/Fail Initializes multi-tile
synchronization feature.
MultiConverter_Sync Type, Latency, Tile Latency, Offsets, Marker
delay, Sysrefenable
To synchronize between tiles.
Table A-1: Command List (Cont’d)
Command Arguments Return Purpose/Comments
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC