Zynq ZedBoard User Manual

1-Aug-2012
15
Table 7 - HDMI Interface Connections
Signal Name
Description
Zynq EPP pin
ADV7511 pin
HDP
Hot Plug Detect signal input
N/C
30
HD-INT
Interrupt signal output
W16
45
HD-SCL
I2C Interface. Supports CMOS
logic levels from 1.8V to 3.3V
AA18
55
HD-SDA
Y16
56
HD-CLK
Video Clock Input. Supports
typical CMOS logic levels from
1.8V up to 3.3V
W18
79
HD-VSYNC
Vertical Sync Input (Not required
if using embedded syncs)
W17
2
HD-HSYNC
Horizontal Sync Input (Not
required if using embedded
syncs)
V17
98
HD-DE
Data Enable signal input for
Digital Video (Not required if
using embedded syncs)
U16
97
HD_D[15:0]
Video Data Input
Bank 35
D0: Y13
D1: AA12
D2: AA14
D3: Y14
D4: AB15
D5: AB16
D6: AA16
D7: AB17
D8: AA17
D9: Y15
D10: W13
D11: W15
D12: V15
D13: U17
D14: V14
D15: V13
88
87
86
85
84
83
82
81
80
78
74
73
72
71
70
69
HD-SPDIF
Sony/Philips Digital Interface
Audio Input
U15
10
HD-SPDIFO
Sony/Philips Digital Interface
Audio Output
Y18
46

Zynq ZedBoard Specifications

General

Processor	Dual-core ARM Cortex-A9
Clock Speed	667 MHz
System Memory	512 MB DDR3
Flash Memory	256 MB
Video Output	HDMI, VGA
Storage	SD Card Slot
FPGA	Xilinx Zynq-7000 XC7Z020
Ethernet	10/100/1000 Mbps Ethernet
USB	USB 2.0 (OTG and Host)
Audio	3.5mm jack, HDMI
Expansion Connectors	FMC, Pmod
Power	5V DC