bdiRDI
JTAG interface for RDI Debuggers, BDI1000 User Manual 18
© Copyright 1999-2003 by ABATRON AG V 1.10
Special BDI Configuration Registers:
In order to change some special configuration parameters of the BDI, the GPR entry in the init list is
used. Normal ARM GPR's covers a range from 0 to 15. Other GPR's are used to set BDI internal
registers:
8005 This entry in the init list allows to change the JTAG clock frequency. This is useful if you have
to start with a slow JTAG clock out of reset but after some initialization (e.g. PLL setup) you
can use a faster clock. As an example see AT91EB55 setup. The value you enter selects the
following JTAG frequency:
0 = adaptive 5 = 200 kHz
1 = 6 MHz 6 = 100 kHz
2 = 3 MHz 7 = 50 kHz
3 = 1 MHz 8 = 20 kHz
4 = 500 kHz 9 = 10 kHz
8006 This entry in the init list allows to define a delay time (in ms) the BDI inserts between releas-
ing the reset line and starting communicating with the target. This delay is necessary when
a target needs some wake-up time after a reset (e.g. Cirrus EP7209).
8007 By default, the BDI asserts the RESET signal during reset processing. After writing zero to
this special register, the BDI no longer drives RESET low. This may be useful in some spe-
cial cases.
8008 During JTAG debugging, the PC increments while the BDI stuffs instruction into the ARM
core. It may be necessary to set the PC to a safe non-vector address before external mem-
ory is accessed to prevent pre-fetching code from an invalid address range. Enter a safe
non-vector address for the PC into this special BDI registers..
8009 By default, the TRST signal is driven with an open-drain driver by the BDI. Write a 1 to this
special BDI register if the TRST signal should be driven with a push-pull driver.
8010 By default, on ARM7 based targets the BDI uses a software breakpoint to support semi host-
ing. In cases where the vector table is allocated to ROM, write a 1 to this special BDI regis-
ters to force the use of a hardware breakpoint. This does not apply to ARM9 targets because
on ARM9 there exists a special vector catch feature.
8012 This entry in the init list allows to define a time (in ms) the BDI asserts the hardware reset
signal. By default the reset signal is asserted for about 3 ms.
8013 With this entry the MAC7100 "JTAG lockout recovery" can be activated. As value enter the
correct CMF clock divider (CMFCLKD). Calculate this value based on the reset frequency,
the frequency that is active before any init list entry is processed (PLL is not active). If for
example the system clock is 8 MHz, the clock input to the flash is 4MHz and the correct value
for CFMCKLD is 19 (0x13). If this entry is present, the BDI automatically recovers a secured
flash as part of the next reset sequence.
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