Advantech PCA-6751 Series - Watchdog Timer Configuration (JP4); Table 1-4: Watchdog Timer System Reset Select (JP4)

Chapter 1 Hardware Configuration 11
1.5.4 Watchdog timer configuration (JP4)
An on-board watchdog timer reduces the chance of disruptions caused
by EMP (electro-magnetic pulse) interference. It is an invaluable
protective device for standalone or unmanned applications. Setup
involves two jumpers and running the control software. (Refer to
Appendix A.)
When the watchdog timer is enabled and the CPU shuts down, the
watchdog timer will automatically either reset the system or generate
an interrupt on IRQ 11, depending on the setting of jumper JP4, as
shown below:
Table 1-4: Watchdog timer system reset select (JP4)
*System reset IRQ 11 interrupt
JP4
* default setting
1
2
3
1
2
3