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Chapter 5 Theory of Operation
Synthesis IC
5
DDS Behavior
DDS waveform generation begins with a high-resolution phase accumulator.
The most significant phase bits are interpolated into four waveform
address streams. These four address streams are then interleaved into
two streams at twice the rate. These two streams become the A_EVN
and A_ODD waveform address lines.
During burst operations, an on-chip counter provides coarse trigger
delay and circuitry that counts waveform cycles and stops the process
when the end of a burst is reached.
Pulse Behavior
“Even” and “Odd” leading- and trailing-edge bit streams are generated in
the Synthesis IC and emitted at the CLK_d2 rate (50 MHz to 100 MHz).
These bit streams are interleaved by the Synchronous Multiplexer into
single leading- and trailing-edge pulses which determine pulse period
and width to within one CLK cycle (5 ns to 10 ns). To achieve better
period resolution the frequency of the clock is varied between 100 MHz
and 200 MHz by the Triggered PLL. To achieve better pulse-width
resolution, a trailing-edge delay vernier circuit (U1505-A, U1506-A,
U1508, and associated components) is employed.
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