118
Chapter 5 Theory of Operation
Clock Divider
5
Clock Divider
See “A1 Clock Divider and Control Schematic” on page 195.
U1101 divides the 800 MHz clock from U903 by two, producing a
differential 400 MHz clock signal, CLKx2±. TRIG_SYNC from the
Trigger Delay circuits goes high briefly when the instrument is
triggered, disabling this divider for a short time to synchronize the
synthesizer with the trigger. U1102 and U1103 divide CLKx2± by 16
to create the 25 MHz frequency reference, TRG_FREF, for the triggered
PLL. U1104 and U1105 form a divide-by-2 circuit that can be disabled by
negating PRI_nTRGe (when the triggered PLL is used) or by asserting
STOPPEDe (when waiting for a trigger).
STOPPEDe also disables the output from the triggered PLL (TRG_VCO±)
at U1106-D. The differential outputs of U1105 (PRI_CLK±) and U1106-D
(TRG_CLK±) are OR-ed together by U1106-A and U1106-B to form
duplicate versions of the clock from which all other waveform-generation
timing is derived. Note that either PRI_CLK± or TRG_CLK±, but not
both, will be active (as determined by the state of PRI_nTRGe).
The output of U1106-A is fed to U1106-C, where it can be disabled by
WFDAC_HOLDe. U1106-C’s differential output (WFDAC_CLK±) clocks
the waveform DAC, U1701, and U1504. It is disabled by WFDAC_HOLDe
to keep the instrument’s output fixed while changing functions.
The complimentary outputs of U1106-B, LOGIC_CLK and LOGIC_CLK*,
provide timing for the remainder of the waveform-generation logic.
LOGIC_CLK is 180° out of phase with WFDAC_CLK to satisfy the
timing requirements of the waveform DAC.
To Next Page
Loading...
Need help?
General
