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Chapter 5 Theory of Operation
Clock Divider
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One half of U1109-A divides LOGIC_CLK by two to create the 100 MHz
signal, CLK_d2e. The other half of U1109-A divides CLK_d2e by two to
create a 50 MHz signal that is delayed by 2.5 ns in U1110 to become
CLK_d4e. CLK_d2e* is gated by U1107-A and U1107-B, then re-clocked
by U1109-B to form two 100 MHz clocks, CLK_d2_ODDe and
CLK_d2_EVNe, that can be individually disabled by negating either
CLK_EN_ODD or CLK_EN_EVN. U1111 translates CLK_d4 and
CLK_d2_ODDe, CLK_d2_EVNe, and CLK_d2e into their TTL
equivalents. CLK_d4 and CLK_d2 are used by the Synthesis IC.
CLK_d2_ODD and CLK_d2_EVN are used by the Waveform RAM.
The state of the flip-flop U1108 determines whether the synthesizer is
“stopped” (waiting for trigger) or “running”. In normal operation, a trigger is
required to start the synthesizer and an assertion of STOP (from the
Synthesis IC by way of the Synchronous Multiplexer) is required to
stop it. When a trigger occurs, TRIG_SYNC is asserted to disable clock
divider U1108, causing STOPPEDe to go low. Then when TRIG_SYNC is
negated, clocks are allowed to propagate to the rest of the system and
synthesis begins. Normally, when STOP is asserted, a “1” is clocked into
U1108 and the system stops. In gated burst mode, however, STOP is
asserted at the end of each waveform cycle, but U1107-D and U1107-E
force U1108’s “D” input low unless the gate signal (TRIGe) is false.
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