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Chapter 5 Theory of Operation
Waveform RAM
5
Waveform RAM
See “A1 Waveform Memory Schematic” on page 197.
There are two banks of waveform RAM, referred to as “ODD” (U1305)
and “EVEN” (U1304). These RAMs perform all operations synchronously.
When writing, address and data are clocked into input latches and then
stored in the memory by on-chip self-timed circuitry. When reading,
address is latched on one clock edge and data is clocked out on the next
clock edge.
U1304 and U1305 have two clock sources. In normal operation they are
clocked at 100 MHz using the CLK_d2_EVEN and CLK_d2_ODD clocks
generated by U1111. When being accessed by the Main CPU or DSP,
they are clocked by WFRAM_CLK from U302.
U1301, U1302, and U1303 are address multiplexers. U1306 and U1307
are data multiplexers. These multiplexers allow the waveform RAM to
be disconnected from the normal signal path and connected to the shared
bus. The multiplexers are “zero-delay” analog switches controlled by
PROG_USE*_EVN and PROG_USE*_ODD from U1201.
CR1301 is placed in the multiplexer’s power supply to lower the supply
voltage to approximately 4.3 V to protect the waveform RAM from higher
signal swings that may be exist on the shared bus.
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