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Chapter 5 Theory of Operation
Trigger and Delay
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Assuming the synthesizer is stopped and triggers enabled, TRIG_ARM
will be high. A rising edge on TRIGe will then clock a “1” into flip-flop
U1007, causing U1008 pin 2 to go “low”, and allowing C1007 to begin
charging in a negative direction through R1049. TRIG_SYNC is also
asserted at this time to disable the synthesizer clocks. Comparator
U1004-B monitors the voltage on C1007 and asserts TRIG_START when
it falls below a threshold set by U1009, U1006, and associated components.
When TRIG_START is asserted, U1007 is reset, thereby negating
TRIG_SYNC and causing C1007 to quickly discharge back to the high
output level of U1008. When the voltage on C1007 rises above the
comparator’s threshold, TRIG_START is negated. When this circuit is
properly calibrated, TRIG_SYNC’s pulse width will vary from a
minimum of 15 ns (corresponding to a 0 ns trigger delay setting) to 55 ns.
TRIG_START’s pulse width is typically 5 ns.
U1009 is a DAC that sets the delay of this circuit by controlling U1004-B’s
threshold voltage. It receives serial data from U1201 via the DAC1_CLK,
DAC1_STRB, and DAC1_DATA lines. U1009’s output, V_TRIGDLY,
ranges from –3 V to +2.5 V (the lower the voltage, the longer the delay).
U1006-B sets the current in Q1001 (from 0 to 120 µA) according to the
difference between V_TRIGDLY and VREF, as buffered by U1006-A.
This current is converted to the comparator’s threshold voltage
(approximately –0.9 V to –1.6 V) by U1006-C.
U1007’s differential output is low-pass filtered and amplified by U1006-D
to form MEAS_TDCAL. The dc voltage on MEAS_TDCAL varies linearly
with TRIG_SYNC’s duty cycle. This voltage is measured by the modulation
A/D converter when the instrument internally calibrates this circuit.
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