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Aim MIL-STD-1553 - Page 118

Aim MIL-STD-1553
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MIL-STD-1553 Reference Manual
104
Chapter 3 System Functions
Start address of the BC acyclic instruction list
A
A
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i
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3
3
2
2
u
u
l
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_
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R
R
e
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p
p
B
B
u
u
f
f
Start address of the Replay buffer
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3
3
2
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u
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l
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_
_
B
B
m
m
B
B
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f
f
Start address of the Bus Monitor buffer
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Y
Y
_
_
A
A
P
P
I
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_
_
M
M
E
E
M
M
_
_
S
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M
M
_
_
B
B
U
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F
F
x
x
_
_
S
S
i
i
m
m
[
[
2
2
]
]
Start addresses and sizes of Simulator data buffers for every Global Memory bank (0..1)
typedef struct ty_api_mem_sim_buf
{
AiUInt32 ul_BufBaseAddr;
AiUInt32 ul_BufSize;
AiUInt32 ul_BufCount;
AiUInt32 ul_HsBufBaseAddr;
AiUInt32 ul_HsBufSize;
AiUInt32 ul_HsRes;
} TY_API_MEM_SIM_BUF;
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B
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a
a
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s
e
e
A
A
d
d
d
d
r
r
Start address of the simulator buffer
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2
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S
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i
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z
z
e
e
Size of the simulator buffer in bytes
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3
3
2
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B
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u
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f
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C
C
o
o
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t
t
Number of data buffers (32 words) in simulator buffer
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3
3
2
2
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H
s
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B
B
u
u
f
f
B
B
a
a
s
s
e
e
A
A
d
d
d
d
r
r
Start address of the HS simulator buffer
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3
2
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H
H
s
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B
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e
e
Size of the HS simulator buffer in bytes
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2
2
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H
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s
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R
R
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s
s
0 (reserved)
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Y
Y
_
_
A
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P
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_
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M
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E
E
M
M
_
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B
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_
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S
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Z
Z
E
E
a
a
x
x
_
_
B
B
i
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u
u
S
S
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z
z
e
e
[
[
8
8
]
]
Size of BC instruction list areas, Replay and BM buffer area (logical BIUs 1..8)
typedef struct ty_api_mem_biu_size
{
AiUInt32 ul_BcHipInstr;
AiUInt32 ul_BcLipInstr;
AiUInt32 ul_BcAcycInstr;
AiUInt32 ul_RepBuf;
AiUInt32 ul_BmBuf;
} TY_API_MEM_BIU_SIZE;
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B
B
c
c
H
H
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Size if the high priority instruction list in bytes
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B
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c
c
L
L
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Size if the low priority instruction list in bytes

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