Alinx AC7015 - Page 9

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ZYNQ FPGA Development Platform AC7015 User Manual
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Figure 3-1: The Schematic part of DDR3 DRAM
Figure 3-2: DDR3 DRAM on the Core Board
DDR3 DRAM Pin Assignment
Signal Name
ZYNQ Pin Name
Pin Number
DDR3_DQS0_P
PS_DDR_DQS_P0_502
C21
DDR3_DQS0_N
PS_DDR_DQS_N0_502
D21
DDR3_DQS1_P
PS_DDR_DQS_P1_502
H21
DDR3_DQS1_N
PS_DDR_DQS_N1_502
J21
DDR3_DQS2_P
PS_DDR_DQS_P2_502
N21
DDR3_DQS2_N
PS_DDR_DQS_N2_502
P21