Alinx AXU2CGA - Page 6

ZYNQ Ultrascale + FPGA Board AXU2CGA/B User Manual
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The main parameters of the PS system are as follows:
 ARM dual-core Cortex™ -A53 processor, speed up to 1.2GHz, each CPU
32KB level 1 instruction and data cache, 1MB level 2 cache, shared by 2
CPUs
 ARM dual-core Cortex-R5 processor, speed up to 500MHz, each CPU
32KB level 1 instruction and data cache, and 128K tightly coupled memory
 External storage interface, support 32/64bit DDR4/3/3L, LPDDR4/3
interface
 Static storage interface, support NAND, 2xQuad-SPI FLASH
 High-speed connection interface, support PCIe Gen2 x4, 2xUSB3.0, Sata
3.1, Display Port, 4 x Tri-mode Gigabit Ethernet
 Common connection interface: 2xUSB2.0, 2x SD/SDIO, 2x UART, 2x CAN
2.0B, 2x I2C, 2x SPI, 4x 32b GPIO
 Power management: support the division of Full/Low/PL/Battery four parts
of power
 Encryption algorithm: support RSA, AES and SHA
 System monitoring: 10-bit 1Mbps AD sampling for temperature and voltage
detection
The main parameters of the PL logic part are as follows:
 Logic Cells: 103K
 flip-flops : 94K
 Lookup table (LUTs) : 47K；
 Block RAM: 5.3Mb
 Clock Management Unit (CMTs) : 3
 Multiplier 18x25MACCs: 240