AT90S2313
20
The most typical and general program setup for the Reset and Interrupt Vector Addresses are:
Address Labels Code Comments
$000 rjmp RESET ; Reset Handler
$001 rjmp EXT_INT0 ; IRQ0 Handler
$002 rjmp EXT_INT1 ; IRQ1 Handler
$003 rjmp TIM_CAPT1 ; Timer1 Capture Handler
$004 rjmp TIM_COMP1 ; Timer1 Compare Handler
$005 rjmp TIM_OVF1 ; Timer1 Overflow Handler
$006 rjmp TIM_OVF0 ; Timer0 Overflow Handler
$007 rjmp UART_RXC ; UART RX Complete Handler
$008 rjmp UART_DRE ; UDR Empty Handler
$009 rjmp UART_TXC ; UART TX Complete Handler
$00a rjmp ANA_COMP ; Analog Comparator Handler
;
$00b MAIN: ldi r16,low(RAMEND); Main program start
$00c out SPL,r16
$00d <instr> xxx
… … … …
Reset Sources
The AT90S2313 has three sources of reset:
• Power-On Reset. The MCU is reset when the supply voltage is below the power-on reset threshold (V
POT
).
• External Reset. The MCU is reset when a low level is present on the RESET
pin for more than 50 ns.
• Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled.
During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The
instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the
program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at
these locations. The circuit diagram in Figure 23 shows the reset logic. Table 3 defines the timing and electrical parameters
of the reset circuitry.
Figure 23. Reset Logic
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