Atmel AT90S2313 - Page 55

AT90S2313
55
Figure 46. Port D Schematic Diagram (Pins PD2 and PD3)
Figure 47. Port D Schematic Diagram (Pins PD4 and PD5)
DATA BUS
D
D
Q
Q
RESET
RESET
C
C
WD
WP
RD
MOS
PULL-
UP
PDn
R
R
WP:
WD:
RL:
RP:
RD:
n:
m:
WRITE PORTD
WRITE DDRD
READ PORTD LATCH
READ PORTD PIN
READ DDRD
4, 5
0, 1
DDDn
PORTDn
SENSE CONTROL
TIMERm CLOCK
SOURCE MUX
CSm2
CSm0
RL
RP
CSm1