AT90S4414/8515
49
UART Status Register - USR
The USR register is a read-only register providing information on the UART Status.
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Bit 7 - RXC: UART Receive Complete
This bit is set (one) when a received character is transferred from the Receiver Shift register to UDR. The bit is set regard-
less of any detected framing errors. When the RXCIE bit in UCR is set, the UART Receive Complete interrupt will be
executed when RXC is set(one). RXC is cleared by reading UDR. When interrupt-driven data reception is used, the UART
Receive Complete Interrupt routine must read UDR in order to clear RXC, otherwise a new interrupt will occur once the
interrupt routine terminates.
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Bit 6 - TXC: UART Transmit Complete
This bit is set (one) when the entire character (including the stop bit) in the Transmit Shift register has been shifted out and
no new data has been written to UDR. This flag is especially useful in half-duplex communications interfaces, where a
transmitting application must enter receive mode and free the communications bus immediately after completing the
transmission.
When the TXCIE bit in UCR is set, setting of TXC causes the UART Transmit Complete interrupt to be executed. TXC is
cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the TXC bit is cleared
(zero) by writing a logical one to the bit.
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Bit 5 - UDRE: UART Data Register Empty
This bit is set (one) when a character written to UDR is transferred to the Transmit shift register. Setting of this bit indicates
that the transmitter is ready to receive a new character for transmission.
When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is
cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt routine
must write UDR in order to clear UDRE, otherwise a new interrupt will occur once the interrupt routine terminates.
UDRE is set (one) during reset to indicate that the transmitter is ready.
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Bit 4 - FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e. when the stop bit of an incoming character is zero.
The FE bit is cleared when the stop bit of received data is one.
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Bit 3 - OR: Overrun
This bit is set if an Overrun condition is detected, i.e. when a character already present in the UDR register is not read
before the next character has been shifted into the Receiver Shift register. The OR bit is buffered, which means that it will
be set once the valid data still in UDRE is read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
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Bits 2..0 - Res: Reserved bits
These bits are reserved bits in the AT90S4414/8515 and will always read as zero.
UART Control Register - UCR
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Bit 7 - RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete interrupt routine to be executed
provided that global interrupts are enabled.
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Bit 6 - TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete interrupt routine to be executed
provided that global interrupts are enabled.
Bit 76543210
$0B ($2B) RXC TXC UDRE FE OR - - - USR
Read/Write R R/W R R R R R R
Initial value 0 0 1 0 0 0 0 0
Bit 76543210
$0A ($2A) RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 UCR
Read/Write R/W R/W R/W R/W R/W R/W R W
Initial value 0 0 0 0 0 0 1 0
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